Tutorial 1: Comprehensive SystemVerilog Verification Solutions for ASIC & SoC Designs
Theme: VLSI Design
Duration: 3.0 Hrs
Speaker: Ashishkumar Christian
Affiliation: ASIC Design and Verification Engineer – eInfochips Ltd, Ahmedabad
About Speaker:Mr. Ashish Christian is working as an ASIC Design and Verification Engineer at eInfochips Ltd, Ahmedabad since 2022. He holds a bachelor’s degree in Electronics and Communication Engineering from Gujarat University (2004) and master’s degree in communication engineering from Sardar Patel University (2012) .
He has 1 year of experience as a Telecom Engineer in ZTE Kangxun Telecom Company India Pvt. Ltd. He has more than 17 years of experience as an Assistant Professor.
He specializes in functional verification of semiconductor IPs, with expertise in Verilog, System Verilog, C and UVM methodologies. He is having experience in IP and SoC Verification. He has worked on the verification on PCIe GEN6 VIP project & Google OpenTitan project. Currently working on HBM4 memory verification. He specializes in verification methodologies, bridging the gap between academic knowledge and industry- aligned practices.
Tutorial Details: Layered Testbench Architecture, Transaction-Level Modelling (TLM) Concepts, Driver, Monitor & Scoreboard Development, Constrained Random Verification Techniques, Functional Coverage & Assertion Integration
Tutorial 2: Embedded ML: From Model Design to Deployment and MLOps for Resource-Constrained Embedded Devices
Theme: Machine Learning
Duration: 3.0 Hrs
Speaker: Ashok Chandrasekaran
Affiliation: Program Director, School of Computing and Data Science, Sai University, Chennai, India
About: Speaker: Dr. Ashok Chandrasekaran (Member, IEEE) is the Program Director of Computer Science at the School of Computing and Data Science, Sai University, Chennai, India. He holds a B.Tech. (Hons.) in Electronics and Communication Engineering with a specialization in VLSI, an M.E. in Communication Systems, a Ph.D. in Array Signal Processing, and a PgCert. in Embedded Systems and Internet of Things from the Indian Institute of Technology Jammu, India. He also serves as an Executive Member of the IEEE Signal Processing Society (SPS) Madras Chapter.
His research interests include array signal processing, sparse sensor array design, source localization and tracking, beamforming, low-rank approximation techniques, and Embedded AI. His current research focuses on TinyML and TinyMLOps for resource-constrained intelligent systems. He has published in reputed IEEE journals and international conferences, including IEEE Communications Letters, IEEE Canadian Journal of Electrical and Computer Engineering, IEEE Signal Processing Magazine (Thesis Column), IEEE TENCON, and the IEEE European Signal Processing Conference (EUSIPCO 2025).
He received the IEEE Publication Award from the IEEE Madras Section in 2021 and 2025. He serves as a reviewer for several journals and conferences, including IEEE Transactions on Vehicular Technology, IEEE Sensors Journal, IEEE Systems Journal, and Progress In Electromagnetics Research. He has also participated in international research activities as a visiting speaker with the DemAI initiative at the BISITE Research Group, University of Salamanca, Spain, and has been associated with the EU-funded CyberChain project.
Dr. Chandrasekaran proposed and organized the IEEE Signal Processing (SP) Cup 2026 Challenge, titled “AV Zoom: Real-Time Audio-Visual Zooming on Smartphones,” held as part of the 51st IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2026), Barcelona, Spain. In collaboration with MathWorks engineers from India and China, he contributed to developing MATLAB starter code for an audio-visual zooming mobile application. He has delivered invited talks at several national and international events.Abstract: Machine learning is increasingly moving from cloud and server-based platforms to resource-constrained edge devices enabling intelligent systems with low latency, reduced communication overhead, improved privacy and real-time decision-making. However, deploying machine learning models on embedded platforms introduces significant challenges related to memory, computational complexity, energy consumption, latency and hardware resources.
This tutorial provides an end-to-end introduction to Embedded Machine Learning (Embedded ML) covering model optimization, deployment and lifecycle management. Participants will explore model optimization techniques including Post-Training Quantization (PTQ), Quantization-Aware Training (QAT), pruning and lightweight neural network architectures such as TinyCONV. The tutorial will also cover model conversion and deployment using TensorFlow Lite/LiteRT, TensorFlow Lite for Microcontrollers and C/C++ implementations supported by practical demonstrations on resource-constrained hardware. A distinctive component of this tutorial is Embedded MLOps covering data and model versioning, automated training and validation, continuous integration and deployment (CI/CD), performance monitoring and model updates. Applications such as keyword spotting and anomaly detection will be used to illustrate practical use cases of Embedded ML.
The tutorial aims to help participants understand the complete process from model design and optimization to deployment and maintenance to build efficient and reliable intelligent edge systems.
Tutorial 3: Quantum Communication as Critical Infrastructure for Power System Operations
Theme: Quantum Communication
Duration: 3.0 Hrs
Speaker: Hillol Biswas
Affiliation: Advisor, Power Division, Senior Member IEEE, Industry, WAPCOS LIMITED, Gurgaon
About Speaker: Hillol Biswas, with a background in software developer, has over three decades of experience across various power-sector disciplines in countries on four continents. Currently focusing on R&D of Power T&D - Cybersecurity, WAPCOS Ltd., Gurgaon, a Govt. of India undertaking, he had been a member of CIGRE since 2006, a senior member of IEEE and the National Academy of Psychology, a life member of the Indian Society of Remote Sensing & the Computer Society of India; his interests are quantum computing, cognitive science, human and machine intelligence, and consciousness studies. As a visiting faculty member at the CBIP Centre of Excellence, Gurgaon, he has delivered lectures and training in industry-specific areas and served as a resource person at academic institutes, ATAL-FDP, and IEEE Tutorials to bridge the gap between industry and academia. He has contributed as an author/reviewer to various IEEE/CIGRE national and international conferences/Springer/Elsevier/Wiley/APA journals/book chapters. ORCID ID: https://orcid.org/0000-0001-5451-4515
Abstract: Smart Grids, i.e., bidirectional power and communication flow, where power flows through overhead conductors/UG cables and Communication through OPGW, are classified as National Critical Information Infrastructure (CII), as Cybersecurity is a concern in Operational Technology (OT) as well. Quantum computing and quantum communication have moved from research to implementation, and real-world power grids are under active study. Worldwide, several initiatives have demonstrated that integrating quantum key distribution (QKD) into power-system communication infrastructure is feasible. How can quantum communication help protect the power grids and critical infrastructures we depend on? This tutorial explores the evolving landscape of quantum communication, from wired fibre networks and satellite links to the cybersecurity of modern power systems. It examines how threats such as GPS spoofing, false data injection, and timing errors could undermine grid stability, and how quantum technologies, combined with conventional communication and post-quantum cryptography, could strengthen security, synchronisation, and real-time situational awareness. Drawing on international utility initiatives, the talk aims to connect emerging concepts with practical deployment challenges, operational realities, and future possibilities. The talk also emphasises standards alignment and practical relevance over mathematical specifics or quantum hardware, given the current state of utility research and implementation.
Tutorial 4: From Miniaturized Mass Spectrometry to Scalable Quantum Computing
Theme: MEMs
Duration: 3.0 hrs
Speaker: Deepak Kumar Sharma
Affiliation: Scientist/Engineer in MEMS foundry of Laboratory for Electro optics systems (LEOS), Indian space research organization (ISRO)
Tutorial Details: Linear ion traps have emerged as one of the most versatile technologies in modern science, enabling revolutionary advances in both miniature mass spectrometry and trapped-ion quantum computing. While originally developed for precise manipulation and analysis of charged particles in analytical chemistry, recent developments in microfabrication, MEMS, and CMOS-compatible processes have transformed linear ion traps into scalable platforms for quantum information processing. This tutorial provides a comprehensive introduction to the physics, design principles, fabrication technologies, and applications of linear ion traps. Beginning with the fundamentals of ion motion in radio-frequency (RF) electric fields, participants will learn the concepts of quadrupole potentials, Mathieu equations, pseudopotential approximation, stability regions, secular frequencies, and ion confinement. The tutorial then explores miniaturized mass spectrometers, covering ion generation techniques, planar linear ion traps, CMOS-compatible fabrication, MEMS integration, miniature vacuum systems, ion detection methods, and performance metrics such as mass resolution and sensitivity.